Semiconductor memory devices have become more highly integrated and operate at higher speeds by significantly reducing the size of memory cells in the devices. Reduced memory cell size has correspondingly reduced the area available for forming transistors and capacitors therein. Accordingly, transistor gate electrode lengths have been decreased.
Decreased transistor gate electrode length can cause a corresponding decrease in the thickness of a gate insulation layer beneath the gate electrode. When the gate insulation layer is formed from silicon oxide (SiO2) and has a thickness of less than about 20 Å, the operation of the transistor may be degraded by an increase in its leakage current due to electron tunneling, infiltration of impurities in the gate electrode, and/or decrease of its threshold voltage.
Capacitor capacitance in the memory cell can decrease as the memory cell decreases in size. Reduction of the capacitance may cause the operation of the memory cell to be degraded by deterioration of data readability in the memory cell, increase in soft error rate, and/or unstable performance of the memory device when operated with a relatively low voltage.
One area of research is directed to developing memory cells with a dielectric layer that has a high dielectric constant. In such memory cells, the gate insulation layer or dielectric layer includes a material having a high dielectric constant, such as tantalum oxide (Ta2O5), yttrium oxide (Y2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), niobium oxide (Nb2O5), barium titanate (BaTiO3), or strontium titanate (SrTiO3).
When the gate insulation layer includes hafnium oxide, it can become crystallized in a subsequent heat treatment process. The gate insulation layer with crystallized hafnium oxide can cause the associated transistor in the in the memory cell to have decreased characteristics due to, for example, increased leakage current, infiltration of impurities contained in the gate electrode, and/or decreased threshold voltage.
In U.S. Pat. No. 6,642,131, a structure includes a layer of hafnium silicon oxide having a high dielectric constant, a lower barrier layer of hafnium silicon oxynitride, and an upper barrier layer of hafnium silicon oxynitride. A semiconductor device having this structure may be prone to having nitrogen exist at an interface between the gate insulation layer and the substrate, which may deteriorate its operating characteristics due to increased defect density and decreased carrier mobility.